Many graphics processing cores may include multiple distinct execution engines (EUs). One EU may be an arithmetic logic unit (ALU) that may perform integer, floating point, and logical operations. Another EU may be a math box which may be dedicated to performing extended math functions such as log, sine, exponent, reciprocal square root etc. Some of the math functions may be implemented in the EUs as ROM pull down logic. Moreover, many of the math functions may be implemented using single instruction, multiple data (SIMD) operations. For SIMD operations, the same instruction may be executed on multiple data.
The graphics processing cores typically include multiple channels or ports for exchanging data with other system components and typically implement duplicative ROM pull down logic for each port. Such duplication may lead to increased chip area size and power consumption. Accordingly, there may be a need for improved techniques to solve these and other problems.